1. Field of the Invention
This invention generally relates to electronic Input/Output (I/O) devices, and, more specifically, relates to a method for configuring multiple identical serial I/O devices to unique addresses through a serial bus.
2. Description of the Related Art
Electronic systems that have components that communicate via a serial bus are well-known in the prior art. When several identical I/O devices are present on the same serial bus, there must be a way to assign each I/O device a unique identification number or address space. This can be accomplished by providing address inputs to each I/O device, and by either hardwiring these inputs to unique values or by driving these inputs to unique values with external logic. However, providing address inputs to uniquely identify each I/O device requires external pins on the I/O device package.
An alternative method of uniquely identifying identical I/O devices is to provide a unique select signal for each I/O device that is activated by external logic when the I/O device needs to be active. This requires an external pin on the I/O device package, and complex circuitry that actively monitors and controls each I/O device, resulting in a system that is more complex and that consumes more power than is desirable.
The trend in electronic systems is towards miniaturization, as shown by the success in the marketplace of laptop and notebook computers, and hand-held video games such as the Nintendo Game Boy. As the size of these systems shrinks, the pin count on their components becomes a significant limiting factor in further decreasing the size of the end product. Many systems are conserving pins by taking certain functions that used to occur in parallel format, and implementing these functions instead in a serial format. In this manner a parallel data transfer that used to take eight data bits and a control bit for handshaking (nine bits total) can be implemented in serial format, which requires only two pins, one for serial data and another for the control bit.
One specific example of reducing pin count by serializing functions previously accomplished in parallel is found in the VL82C480 chipset by VLSI. To minimize the number of pins required to support a traditional ISA bus, the VL82C480 put the DMA Request (DRQ) and Interrupt Request (IRQ) inputs that service the ISA bus into a parallel to serial converter, and used the resulting serial stream to determine the state of the DRQ and IRQ inputs. This serial stream had a dedicated bit for each DRQ and IRQ input. This serialization of DRQs and IRQs introduces latency to these signals due to the time required to serialize the data, the time required to shift out this data serially, and the time required to convert this serial data back to parallel format. For the case of a DMA Request, excessive latency could result in the DRQ input being asserted after the service of the DMA is no longer required, resulting in overflowing or underflowing the DMA data transfer. For the case of an Interrupt Request, excessive latency could cause the IRQ input to be asserted when an interrupt is no longer present, resulting in the CPU servicing the Interrupt Request needlessly. For these reasons the latency of the serial stream is critical and must be minimized.
In today's miniature electronic systems, which are typically battery-powered, the pin count of components, total parts count and size, and power consumed are of primary importance. The additional pins required to differentiate in hardware between identical I/O devices increases the total pins on the I/O device. If external logic is used to differentiate between identical I/O devices, this logic adds complexity, uses precious real estate on the printed circuit boards, and consumes power.
Therefore, there existed a need to provide a method for configuring identical I/O devices which communicate on a common serial bus without using any additional pins or external logic, and which provides minimum latency for the signals on the serial bus.